1. Field of the Invention
This invention relates generally to buffers. More particularly, it relates to integrated circuits (ICs) including low voltage buffers, e.g., 2.5 volt buffers having high current and/or voltage tolerance.
2. Background of Related Art
In computer systems, the reduction of power usage is paramount. Initially, many computer buses (e.g., SCSI, DDR, PCI, PCMCIA, etc.) were based on 5 volt standards. More recently, the voltage level of those standards has been lowered to 3.3 volts. The lower voltage provides significant power savings, lowers capacitance between lines, and other advantages.
However, in lowering the voltage standard to 3.3V, many existing system components would have been rendered useless but for requirements that the new, lower voltage systems be backwards compatible to accommodate 5V components. Thus, system components generally powered at only 3.3V needed to communicate with system components that were powered at 5V. The terminology referring to this backwards compatibility for 5V legacy systems is commonly referred to as “5V tolerant” systems.
Various system components communicate with one another typically via wired lines or busses. To buffer various components, input and/or output buffers are typically established at the input or output of any line in communication with the bus or lines to another system component. Many systems have bi-directional communication lines, and bi-directional buffers are appropriately used.
5V tolerant, 3.3V buffers have been known. For instance, FIG. 7 shows a portion of an integrated circuit including conventional 5V tolerant open drain buffer made with 3.3V technology MOS transistors.
In particular, as shown in FIG. 7, VDD represents the power supply, and VSS ground. An inverter formed by a series connection of a p-channel Field Effect Transistor (FET) M1 and an n-channel FET transistor M2 drives node N to the opposite voltage of the input signal A. An output stage comprises a series connection of two n-channel FET transistors M3 and M4. The gate of transistor M3 is connected to node N, while the gate of transistor M4 is connected to the power supply VDD.
In operation, when signal A is LOW, node N goes HIGH, turning transistor M3 ON and pulling PAD LOW, since transistor M4 is always ON. When signal A is HIGH, node N is driven LOW, turning transistor M3 OFF.
If a 5V signal is applied to PAD when signal A is HIGH, transistor M4 protects transistor M3 by acting as a source-follower. Thus, when PAD is at 5V, transistor M4 does not allow node N1 to go below VDD-Vtn, where Vtn is the n-channel threshold of transistor M4. This value is typically 0.8V. With a nominally 3.3V+/−10% power supply (VDD=3.3V), the voltage at node N1 cannot go below 3.0V−0.8V=2.2V. On the other hand, with a maximum voltage of 5V+10%=5.5V on PAD (high end range of a nominally 5.0V power supply), this limits the drain-to-source voltage on transistor M4 to 5.5V−2.2V=3.3V.
In the never-ending quest to lower power consumption and increase the speed of electronic and computer systems, lower voltage standards are being developed, most notably a 2.5V standard. Over the years this standard may drop to 2.0V, and even to 1.8V. For such low voltage systems to maintain support for and compatibility with legacy systems, it is desirable for 2.5V systems to be capable of communicating and fully operable with systems using nominal 5V and 3.3V power supplies. However, significant hurdles exist for such ultra low voltage 2.5V (and less) systems to be tolerant to 5V inputs or outputs.
For instance, while power supplies have a nominal voltage of, e.g., 5V or 2.5V, etc., power supplies typically exhibit a tolerance in voltage variation of +/−10%. Tight tolerances on a power supply dramatically increases costs of the power supply. As in everything, there is a balance between acceptable tolerance and price. Many power supplies are considered acceptable with a +/−10% tolerance. Thus, even though a power supply might be nominally rated for 2.5V, it can be as low as 2.25V. Similarly, even though a 5.0V system is nominally rated for 5.0V, it can be as high as 5.5V.
Referring again to the conventional buffer 500 shown in FIG. 7, if VDD were to be lowered to only 2.25V, then node N1 can go as low as 2.25V−0.8V=1.45V. This generates a drain-to-source voltage on transistor M4 equal to 5.5V−1.45V=4.05V. This voltage of over 4 volts significantly exceeds the high end technology limit of 3.63V for 3.3V technology. Thus, the transistors of the buffer 500 would be damaged if VDD were an in-spec 2.25V and an in-spec 5.5V legacy system were connected to the buffer 500.
Current 5V tolerant buffers manufactured using 3.3V technology require a 3.3V power supply to assure that no transistor sees a gate voltage or drain-to-source voltage greater than 3.63V. There is a need for an integrated circuit having a 5V tolerant buffer design that can be powered with a power supply voltage significantly lower than 3.3 V, e.g., of only a 2.5V (or lower voltage).